The design of an integrated circuit (IC) requires that a layout be designed which specifies the arrangement of the various circuit components on the major surface of a semiconductor substrate, for example a silicon crystal.
Since many circuit elements are repeatedly utilized, these circuit elements are reduced to cells. The layout can be generated by arranging the cells and connecting them using conductive interconnects. Layout is usually performed utilizing sophisticated software tools well-known to persons of skill in the art.
The layout of the interconnects is a complex geometrical problem. However, in high frequency ICs the layout must also account for electromagnetic effects, which cause parasitic resistance and capacitance which can degrade the performance of the IC.
FIG. 1 depicts the standard design of a cell 10, a layout of two cells, and the interconnection of the cells where each cell 10 includes an inductor region 12, a resistor region 14, and a transistor region 16. An example of such a circuit is disclosed in the aforementioned application.
In FIG. 1 a first set of conductive lines 18 couples the inductor region 12 to the resistor region 14 and a second set of conductive lines 20 connects the resistor region 14 to the transistor region 16. A set of cell to cell signal interconnects 22 couples the output nodes of the first cell to the inputs of the transistor region of the second cell. All the regions 12, 14, and 16 are rectangular and have a characteristic lateral dimension: DI for the inductor region 12, DR for the resistor region 14, and DT for the transistor region. As is apparent from FIG. 1, the lateral dimension of the cell 10 is about equal to the dimension of the largest circuit element, in this case the inductor, and is about equal to DI. Because of the symmetrical design of the inductor, resistor regions, and transistor regions, the regions tend to be aligned and the length of the conductive lines connecting the regions minimized. The length of the cell-to-cell interconnects, which transmit high frequency signals, is thus very long because of the large lateral dimension of the inductor compared to the other regions.
In very high frequency applications, the interconnect parasitic resistors and capacitors form an RC network that plays a very important role. This RC network attenuates the high frequency clock and creates Inter-Symbol Interference (ISI) jitter on the data. These effects become even more important for C3MOS cells with inductive broadbanding. (The presence of the inductors in these cases changes the RC networks to RCL networks). As described above and in the referenced patent, the load here includes an inductor in series with a resistor. Since the physical size of the inductor is typically an order of magnitude bigger than the physical size of the resistor, these cells require a small area for transistors and resistors and a very large area for inductors. As depicted in FIG. 1, this makes the cell-to-cell interconnects 22 very long. Since the length of the interconnects is directly proportional to their parasitic resistance and capacitance, whatever speed improvement is gained through inductive broadbanding can be lost due to these additional parasitic effects if the layout is not done carefully. Moreover, if the inductors are close to metal or active areas, magnetic coupling further degrades the speed improvement.